π -> 02/14/25: ECS154A-L17
π€ Vocab
β Unit and Larger Context
How to build a machine? Microarchitecture
βοΈ -> Scratch Notes
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Minimal example of CPU, capable of executing instructions
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X and Z are buffers, to hold the data and prevent signals from mixing (bus canβt hold A and B at same time, need temp storage in X) (same with Z)
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FDE Cycle:
- Fetch - Gets the instruction
- Decode - Decodes the fetched information, translates it
- Execute - Does what the instruction told it to
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Going through this cycle is effectively a big Moore model, going through the states of each step.
Example Steps for Instructions
| Cycle | Instructions | |||
|---|---|---|---|---|
| 0 | PC -> Bus ( | Bus -> MAR ( | Send the READ signal | BUS -> X ( |
| 1 | INC B ( | |||
| 2 | Z -> Bus | Bus -> PC | ||
| 3 | MDR -> Bus | Bus -> IR | ||
| 4 | ACC -> Bus | Bus -> X | ||
| 5 | R -> Bus | ADD | ||
| 6 | Z -> Bus | Bus -> ACC |
- Instructions for ADD R
- ADD R: ACC = ACC + R
| Cycle | Instructions | ||
|---|---|---|---|
| n | R -> Bus ( | Bus -> MAR ( | Send the READ signal |
| n+1 | ACC -> Bus | Bus -> X | |
| n+2 | MDR -> Bus | ADD | |
| n+3 | Z -> Bus | B -> ACC | |
| n+4 | |||
| n+5 |
- Instructions for ADD mem(R)
- ACC (R): CC = ACC + mem(R)
Comparison:
ADD R takes 3 execute cycles
ADD (R) takes 4 execute cycles
We can see that the limiting factor here is sharing the bus. Multiple buses could mean faster execution!
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- Visualized as a Moore Model
Continuation
You can speed it up by adding another bus! Or another! Or another!


With 3 buses, you can do the entire instruction of add in ONE cycle!
CISC - Complex Instruction Set Computer
RISC - Reduced Instruction Set Computer
Which is faster?
- Define faster!
- CISC has more instructions than RISC, but RISC manages them better.
π§ͺ -> Refresh the Info
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