ECS154A-L20

Filling in cramming post final

Memory is a linear array of storage cells

Transclude of ECS154A-L20-2025-03-18-23.06.36.excalidraw

• Doing a 4 bit entry for simplicity
• Horizontal are called word lines
• Vertical are bit lines
• The decoder will produce a 1-hot code
• A control signals (Address Lines) will map to 2^N decoder

Memory

2 Kinds of VolatileMemory

• Static + Dynamic
  • Static is FF
    • Cross coupled NOT
  • Dynamic is transistors
    • Pass transistor?
    • When the word line turns on, all of the bits associated with that word line wil connect their capacitor to the bit line, either pulling it to ground or charging it up
      • They kind of make a tri state device, being disconnected until word line turns on
    • Very small, bucket of electrons
    • Reading, dump onto word line bus
    • Destructive readout. When you read out the value, you need to refresh the data afterwards. This makes it slow.
      SRAM:
• Hot
• Fast
• Not dense
  DRAM:
• Cool
• Slow
• Dense
• Approaching end of life, cannot make them slower

Cache:

• Write into memory address register
• Clarify read or write

To tell if address in cache matches target address, do a comparison.
XOR the two addresses, and if the result is zero, we have a match