ECS154A-L24

📗 -> 03/05/25: ECS154A-L24

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[Lecture Slide Link]

🎤 Vocab

❗ Unit and Larger Context

Small summary

✒️ -> Scratch Notes

Segment Table

• Get stuff
  Indexed by left most
  Bits of adders

Suppose we have a segment table:
Present, PT adders

	P				PT0	PT1	PT2	PT3
00	1	00		00	110	100	111	100
01	0	10		01	101	101	111	000
10	1	11		10	001	010	101	001
11	1	01		11	000	111		100

• Segment table, then page tables

  • My page table entries might not be accurate, board is far

• Add 100110

  1. Look at segment table number 2
  2. It tells us to go to PT3
  3. We look at the 01 entry, and we …
     If segment table does not have entry, we get the message “Segmentation Fault: Core Dumped”

• The iconic seg fault! It dumps the memory onto a tape/disk, and then programmers could figure out what went wrong

• We need the seg fault so that not all programs can run around and do OS things

  • Protect user profiles on machines for instance
    Different than a page fault:

• Seg fault is irrecoverable

• Page fault means we just have to go to memory

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CPU/ Mem

• We want a cache of recent Virtual-Physical (V-P) translations

IBM calls caches “Lookaside buffers”
-> Because of this, the V-P table is called Translation Lookaside Buffers (TLB)

Regular cache (data cache?), we send addresses to. The TLB tells us what the addresses should be. Give virtual addresses to the cache, and if there’s a miss, send it to the TLB, then memory.

• The problem with this scheme, is that every process starts at the same virtual address (4000).
• This means that we can have incorrect hits, as the address might belong to another program.
• This is called aliasing

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TLB 128 entries
8k byte pages -
2mb cache -
256 pages in 2mb cache.

• Chance of getting a miss, and then finding out it was in there the whole time

Need to know

Processor design
Bus design
Tristate stuff
Can’t connect outputs
Microcoding

Performance

• Measure
• Benchmark
  CPU equation
  Ahmdahs law

Memory
Static vs Dynamic

• Compare
• Adv and Disadv

Cache
Localities, different kinds
Goals of caching
Make it out of the cheap stuff, perform like the fast stuff

Right policies, line sizes, why writes are slower than reads (state changes)
Average access time euqation being more important than miss rate

Virtual Memory
Why it’s necessary

Page frames, page table entries, etc.
What a TLB is, why its neccessary, what a pag etable walk is.

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Q&A

Dirty Bit - When you have a cache, you write to memory, you expect it in there. In a write back cache, its stuck halfway in cache. need to tell cache when something needs to be written to main memory
Dirty bit indicates that a line in a cache has been written to.

If you break table into smaller sections, you don’t need to allocate as much space to every process.

• Because of locality, splitting up and usign table
• Base page table is the only one that has to be in memory at all times
  • Probably / generally null most of the time.
  • Less than the unbroken strategy

Microcoding, filing out the table of activating bus, PCin etc. - described on home page

Write hit:

1. Write through
   • No dirty bit, but very very slow
2. Write back
   • This is the one that requires the dirty bit
   • Most caches follow this one
     Write Miss
     Didn’t find it, should I go out and bring it in and cache it? Or not?

• Important, if new data needs to be cached, old data should be thrown out

1. Allocate

2. No allocate

Armahld’s Law
Int takes 80% -> 60% (90%)
F takes 20% -> 90% (10%)

(80-10) + 20 = 52
80 + (20 + 1) = 82

Size * speed up that makes the difference. Not just which one is bigger

🧪 -> Refresh the Info

Did you generally find the overall content understandable or compelling or relevant or not, and why, or which aspects of the reading were most novel or challenging for you and which aspects were most familiar or straightforward?)

Did a specific aspect of the reading raise questions for you or relate to other ideas and findings you’ve encountered, or are there other related issues you wish had been covered?)

🔗 -> Links

Resources

• Put useful links here

Connections

• Link all related words