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ECS154A-L25

3 min read

📗 -> 03/07/25: ECS154A-L25

[Lecture Slide Link]

🎤 Vocab

❗ Unit and Larger Context

Small summary

✒️ -> Scratch Notes

Pipelining

Doing laundry example:

  • Wash = 40
  • Dry = 50
  • Fold = 30
    6 => 330m

WDF
-WDF
—WDF
---WDF
…

You have to wait for the longest thing to occur. So in this example, we have to wait 50 minutes in each pipeline cycle, even though folding finishes in 30.

Balanced pipeline:

  • WCP (longest stage) is approximately equal for all
    In the above situation its not balanced 40|50|30 is not equal for all.
    Instead, find ways to balance the work.
  • He suggests taking the clothes out at 40 minutes and drying them with a hairdryer for 10 minutes so we have a 40|40|40 pipeline afterward. Cheeky.
  • Now after balancing, we go from 300 -> 240 minutes.

FDE in computer:

FDE M W?

  • Chat GPT said:
    • M (Memory access): This stage involves reading from or writing to memory.
    • W (Write-back): This stage writes the result back to a register.
      Fetch: instruction
      Decode: instruction
      Execute: instruction
      Memory: access if needed
      Write: back to register file.
12345
FDEMW
-FDEMW
--FDEMW
---FDEMW
...
  • Takes longer than a 3 cycle FDE (higher latency), but the upside is throughput
    • Now, we take until the 5th cycle to write our result, but we produce a response every cycle following that. Increases throughput.
Hazards:
  • Structural - Resource conflict
  • Data - 3 types
  • Control - change in control flow

Structural - Problems come from shared resources

  • Can often be fixed by spending more money
  • IE, adding another memory (data memory and instruction memory) to speed up cycle/execution time

Examples will be in form: Instruction Destination Source1 Source2
ADD R1, R2, R3
SUB R1, R2, R3

123456
FDEMW
-FDEMW
How can we write R1?

  • It happens in cycle 5: Write
  • It gets read in 2: Decode
    • The 2 that gets read is a RAW hazard
      If we read after writing (say a register when adding), we get a read after write hazard (RAW hazard)

Note: D=Decode + Read Regs

To allow writing and decoding/reading from registers on the same cycle:

  • Write on 1st half
  • Read on 2nd half

How to avoid:

  • Forwarding / Bypassing
    • Forwarding the result to whatever needs it. Needs extra hardware, but removes NOPs.

In more complex pipelines where you can do your own instructions, you also have to worry about write after write hazards (WAW hazard)

1234567
FDEEMMW
-FDEEW

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